50 Commits

Author	SHA1	Message	Date
HerveDelseny	75c579f51f	Add files via upload	2018-02-15 08:59:59 +01:00
HerveDelseny	eb7eb92349	Add files via upload	2018-02-14 11:57:14 +01:00
fpothon	8a717e7248	Add files via upload	2018-02-14 09:49:58 +01:00
pfarail	876e1c798a	Finalisation of the use case description from FP	2018-02-13 15:08:35 +01:00
Emmanuel Ledinot	58c28347d3	Delete Case study Multisystem Integration.doc.doc	2018-02-13 00:38:53 +00:00
Emmanuel Ledinot	a3ba6c20a5	Add files via upload	2018-02-13 01:38:10 +01:00
Emmanuel Ledinot	7d458bb3ed	Add files via upload	2018-02-13 01:36:40 +01:00
fpothon	c9cc833fc3	Add files via upload	2018-01-30 14:15:15 +01:00
HerveDelseny	8933abb375	Delete Case study template FPGA Development_2.doc ... File renamed in Case Study FPGA Development	2018-01-19 15:34:40 +00:00
MiguelDeAlmeida	3d7f65fce0	Add files via upload	2018-01-19 14:39:24 +01:00
MiguelDeAlmeida	e57b96aa32	Add files via upload	2018-01-11 14:34:53 +01:00
MiguelDeAlmeida	25363477d6	Delete Case study template Soc Development.doc	2018-01-11 13:34:02 +00:00
ThalesAV	1ac44805e3	Add files via upload	2018-01-11 11:43:49 +01:00
ThalesAV	1b2aa52b71	Delete Case Study HW COTS AEH_Process Description_1.2.1.doc	2018-01-11 10:42:11 +00:00
ThalesAV	8b2dcb6a73	Delete Case Study HW COTS AEH_Properties Mapping_1.1.0.doc	2018-01-11 10:41:39 +00:00
AP Porte	61ae698055	update during january 11th meeting	2018-01-11 11:35:30 +01:00
ThalesAV	1ee652880b	Delete Case Study HW COTS AEH.doc	2018-01-11 10:29:36 +00:00
ThalesAV	d224b4bd5b	Delete Case Study HW COTS AEH selection__process_1.1.doc	2018-01-11 10:28:23 +00:00
ThalesAV	b7513db80c	Add files via upload	2018-01-11 11:25:01 +01:00
fpothon	7f182ab2cb	Add files via upload	2018-01-10 15:55:51 +01:00
AP Porte	c14d7900a0	ressac meeting january 9th	2018-01-09 18:14:55 +01:00
Anthony Leonardo Gracio	cfd1c3007d	Update the Case study SPARK document ... In particular define more precisely what are the SPARK global contracts and specify which errors can be found (and how) during the different phases of the project (software requirements development, etc.).	2018-01-08 17:15:48 +01:00
AP Porte	b1e1b28dcd	update of the software model process definition in preparation of the january meeting	2018-01-08 15:28:32 +01:00
fpothon	27701e9d4b	Add files via upload	2017-12-29 11:07:14 +01:00
fpothon	b3ba4d5e81	Add files via upload	2017-12-15 16:40:48 +01:00
AP Porte	d474d6ae5d	dec 14th commit ... advanced in group on - inputs/outputs of system processes, in the synthesis table; to move to the sections - information in the software development processes	2017-12-14 15:05:31 +01:00
MiguelDeAlmeida	42bead4a42	Add files via upload	2017-12-14 14:44:23 +01:00
HerveDelseny	54edb3cc12	Another step after Dec17 workshop ... Context part, scheme, and 1st activity have been reviewed and improved => next step consists in continuing description of the other activities in the same way.	2017-12-14 12:34:48 +01:00
AP Porte	c8d122e3e6	2017 dec 14th changes ... move error classes and means from synthesis table defined in group on dec 13th into the sections; remains to define inputs/outputs	2017-12-14 10:22:14 +01:00
AP Porte	cf06e94c76	dec 13th meeting ... added a synthesis table for system definition to cover all activities and the error classes they introduce, to clarify need to add in each chapter - inputs/outputs of each activity - details of each activity - complete the error classes of each activity from the synthesis table synthesis table to remove from document when activities descriptions are complete.	2017-12-13 17:29:36 +01:00
AP Porte	027f035513	december meeting 13/12 ... after exchange	2017-12-13 16:03:15 +01:00
fpothon	57747a4300	Add files via upload	2017-12-13 11:39:41 +01:00
fpothon	def6bfa151	Add files via upload	2017-12-12 17:25:49 +01:00
HerveDelseny	109b6e1f0a	Add files via upload	2017-11-29 10:27:48 +01:00
HerveDelseny	28533433f9	Add files via upload	2017-11-29 10:25:05 +01:00
AP Porte	ff1290968d	Add files via upload ... add a summary of last discussion of nov 16th meeting	2017-11-16 18:05:05 +01:00
AP Porte	307a9f7634	process diagram changed	2017-11-16 15:48:23 +01:00
HerveDelseny	80dcc15d1e	Add files via upload	2017-11-16 14:25:47 +01:00
HerveDelseny	0c9150d646	Delete Case Study HW COTS AEH -16 Nov 2017.doc	2017-11-16 14:23:17 +01:00
AP Porte	25cbda2e6c	added SW integration process - to complete	2017-11-16 14:22:42 +01:00
HerveDelseny	552441ae70	Add files via upload	2017-11-16 14:21:52 +01:00
AP Porte	54f4ed0f91	results of N.C & E.L work + review in group	2017-11-15 17:57:32 +01:00
AP Porte	c8807a15c1	to rename it consistently	2017-11-15 17:56:26 +01:00
AP Porte	8b832596f5	result of work by NC & EL + review in group	2017-11-15 17:55:17 +01:00
AP Porte	892a2e5da3	update on 2017/11/15 afternoon ... added software processes	2017-11-15 16:52:26 +01:00
AP Porte	a8849a15a3	Result of workshop 2017/11/15 morning ... add schema behavioral model simulations error classes	2017-11-15 12:47:49 +01:00
fpothon	5bc4b40806	Updated on 2017 November 14, day 1 Resac meeting	2017-11-14 17:52:44 +01:00
pfarail	998b9a7177	Adding template for use case form	2017-11-14 17:44:00 +01:00
SylvanDissoubray	70883242d4	Add files via upload ... Working session APP/SD	2017-11-10 10:57:30 +01:00
CyrilleComar	b914e6c263	reorg ... big reorganization agreed during 2017-10-26	2017-10-26 15:28:50 +02:00