8a717e7248
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8 years ago
876e1c798a
Finalisation of the use case description from FP
8 years ago
58c28347d3
Delete Case study Multisystem Integration.doc.doc
8 years ago
a3ba6c20a5
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8 years ago
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8 years ago
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8 years ago
8933abb375
Delete Case study template FPGA Development_2.doc
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File renamed in Case Study FPGA Development
8 years ago
3d7f65fce0
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8 years ago
e57b96aa32
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8 years ago
25363477d6
Delete Case study template Soc Development.doc
8 years ago
1ac44805e3
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8 years ago
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Delete Case Study HW COTS AEH_Process Description_1.2.1.doc
8 years ago
8b2dcb6a73
Delete Case Study HW COTS AEH_Properties Mapping_1.1.0.doc
8 years ago
61ae698055
update during january 11th meeting
8 years ago
1ee652880b
Delete Case Study HW COTS AEH.doc
8 years ago
d224b4bd5b
Delete Case Study HW COTS AEH selection__process_1.1.doc
8 years ago
b7513db80c
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8 years ago
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8 years ago
c14d7900a0
ressac meeting january 9th
8 years ago
cfd1c3007d
Update the Case study SPARK document
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In particular define more precisely what are the SPARK global contracts
and specify which errors can be found (and how) during the different
phases of the project (software requirements development, etc.).
8 years ago
b1e1b28dcd
update of the software model process definition in preparation of the january meeting
8 years ago
27701e9d4b
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8 years ago
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8 years ago
d474d6ae5d
dec 14th commit
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advanced in group on
- inputs/outputs of system processes, in the synthesis table; to move to the sections
- information in the software development processes
8 years ago
42bead4a42
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8 years ago
54edb3cc12
Another step after Dec17 workshop
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Context part, scheme, and 1st activity have been reviewed and improved => next step consists in continuing description of the other activities in the same way.
8 years ago
c8d122e3e6
2017 dec 14th changes
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move error classes and means from synthesis table defined in group on dec 13th into the sections;
remains to define inputs/outputs
8 years ago
cf06e94c76
dec 13th meeting
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added a synthesis table for system definition to cover all activities and the error classes they introduce, to clarify
need to add in each chapter
- inputs/outputs of each activity
- details of each activity
- complete the error classes of each activity from the synthesis table
synthesis table to remove from document when activities descriptions are complete.
8 years ago
027f035513
december meeting 13/12
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after exchange
8 years ago
57747a4300
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8 years ago
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8 years ago
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8 years ago
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8 years ago
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add a summary of last discussion of nov 16th meeting
8 years ago
307a9f7634
process diagram changed
8 years ago
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8 years ago
0c9150d646
Delete Case Study HW COTS AEH -16 Nov 2017.doc
8 years ago
25cbda2e6c
added SW integration process - to complete
8 years ago
552441ae70
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8 years ago
54f4ed0f91
results of N.C & E.L work + review in group
8 years ago
c8807a15c1
to rename it consistently
8 years ago
8b832596f5
result of work by NC & EL + review in group
8 years ago
892a2e5da3
update on 2017/11/15 afternoon
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added software processes
8 years ago
a8849a15a3
Result of workshop 2017/11/15 morning
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add schema
behavioral model
simulations
error classes
8 years ago
5bc4b40806
Updated on 2017 November 14, day 1 Resac meeting
8 years ago
998b9a7177
Adding template for use case form
8 years ago
70883242d4
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Working session APP/SD
8 years ago
b914e6c263
reorg
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big reorganization agreed during 2017-10-26
8 years ago
fpothon
pfarail
Emmanuel Ledinot
HerveDelseny
MiguelDeAlmeida
ThalesAV
AP Porte
Anthony Leonardo Gracio
SylvanDissoubray
CyrilleComar