File renamed in Case Study FPGA Development

this is for external communication purposes.

move README to new organization

In particular define more precisely what are the SPARK global contracts
and specify which errors can be found (and how) during the different
phases of the project (software requirements development, etc.).

advanced in group on 
 - inputs/outputs of system processes, in the synthesis table; to move to the sections
 - information in the software development processes

Context part, scheme, and 1st activity have been reviewed and improved => next step consists in continuing description of the other activities in the same way.

move error classes and means from synthesis table defined in group on dec 13th into the sections;
remains to define inputs/outputs

added a synthesis table for system definition to cover all activities and the error classes they introduce, to clarify
need to add in each chapter 
 - inputs/outputs of each activity
 - details of each activity
 - complete the error classes of each activity from the synthesis table
synthesis table to remove from document when activities descriptions are complete.

after exchange

An initial version of SysML SCADE Architect MMS Architecture DRAFT. This report will be merged into RESSAC_muXAV_SystemRQ_MMS_SW_Incr1.doc.

add a summary of last discussion of nov 16th meeting