- 13 Feb, 2018 5 commits
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pfarail authored
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Emmanuel Ledinot authored
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Emmanuel Ledinot authored
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Emmanuel Ledinot authored
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Emmanuel Ledinot authored
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- 08 Feb, 2018 4 commits
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SylvanDissoubray authored
File MMS-SRATS_in-progress.docx is a current rework of MMS system Specification, with reorganized contents, tags, and a few remining issues not solved.
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SylvanDissoubray authored
Folder muXAV_v3_removed_propagation_across contains a SysML SCADE Architect model of muXAV wdetailed on the MMS part. Data are propagated but not through F_CM where data change needs to be represented in model. This model is starting point candidate to refine organic architecture by an AADL model (the SysML model can contain plain SCADE Architect and SCADE AADL models in same model but dedicated packages).
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SylvanDissoubray authored
Folder MMS contans SCADE Suite MMS model (essentially F_FC, flight control parts). MMS_Interface_Synchro contains the MMS top level synchronization between SCADE Suite and SCADE Architect
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fpothon authored
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- 30 Jan, 2018 1 commit
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fpothon authored
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- 19 Jan, 2018 2 commits
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HerveDelseny authored
File renamed in Case Study FPGA Development
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MiguelDeAlmeida authored
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- 11 Jan, 2018 9 commits
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MiguelDeAlmeida authored
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MiguelDeAlmeida authored
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ThalesAV authored
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ThalesAV authored
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ThalesAV authored
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AP Porte authored
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ThalesAV authored
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ThalesAV authored
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ThalesAV authored
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- 10 Jan, 2018 3 commits
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fpothon authored
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CyrilleComar authored
this is for external communication purposes.
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CyrilleComar authored
move README to new organization
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- 09 Jan, 2018 1 commit
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AP Porte authored
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- 08 Jan, 2018 8 commits
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Emmanuel Ledinot authored
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Emmanuel Ledinot authored
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Emmanuel Ledinot authored
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Emmanuel Ledinot authored
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Anthony Leonardo Gracio authored
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Anthony Leonardo Gracio authored
In particular define more precisely what are the SPARK global contracts and specify which errors can be found (and how) during the different phases of the project (software requirements development, etc.).
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Anthony Leonardo Gracio authored
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AP Porte authored
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- 29 Dec, 2017 1 commit
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fpothon authored
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- 15 Dec, 2017 1 commit
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fpothon authored
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- 14 Dec, 2017 4 commits
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AP Porte authored
advanced in group on - inputs/outputs of system processes, in the synthesis table; to move to the sections - information in the software development processes
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MiguelDeAlmeida authored
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HerveDelseny authored
Context part, scheme, and 1st activity have been reviewed and improved => next step consists in continuing description of the other activities in the same way.
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AP Porte authored
move error classes and means from synthesis table defined in group on dec 13th into the sections; remains to define inputs/outputs
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- 13 Dec, 2017 1 commit
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AP Porte authored
added a synthesis table for system definition to cover all activities and the error classes they introduce, to clarify need to add in each chapter - inputs/outputs of each activity - details of each activity - complete the error classes of each activity from the synthesis table synthesis table to remove from document when activities descriptions are complete.
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